Platform Based SRAM Sleep Power Minimization

Abstrac t  As Complementary Metal-Oxide-Silicon (CMOS) technology scales its critical dimensions, it imposes negative impacts on digital circuit performance mainly in two aspects: leakage and variability. It is widely believed that Static Random Access Memory (SRAM), among all digital circuits, is most susceptible to these impacts. Attempting to accommodate leakage and process variability in a systematic fashion, we propose a platform based design methodology for SRAM power minimization at sleep mode. A meet-in-the-middle approach, platform base design maps high-level performance requirements (such as speed and area) to lower-level process parameters (such as threshold voltage and sub-threshold slope), and yields a set of circuit variables (such as device width and body bias voltage) that produce minimum sleep power. When process variation is properly modeled, the proposed approach can be employed to predict fabrication yield and more importantly, to re-design circuit parameters so that the resulted SRAM is more tolerant of process variations.